1. Field of the Invention
The present invention relates to a semiconductor circuit device, and particularly to a semiconductor circuit device assembled into a plurality of types of packages. More particularly, the present invention relates to the configuration of a semiconductor memory device with a common chip configuration allowing assembly into a plurality of types of packages.
2. Description of the Background Art
A semiconductor circuit formed on a semiconductor chip is assembled into a package before shipment as a final product. The semiconductor circuit is electrically connected to on-board wires through a pin terminal of the package, or the package protects the semiconductor chip against external contamination sources and external destructive factors such as external mechanical stress and external electromagnetism.
Various types of packages are prepared according to the configuration of applicable board systems. Recently, a package referred to as “surface mount device (SMD)” has been widely employed so as to mount semiconductor circuits on both sides of a board.
FIG. 72 is a schematic diagram showing the appearance of a TSOP (thin small outline package) which is one of conventional SMDs. In FIG. 72, TSOP has an internal semiconductor chip sealed with a mold resin MRJ. Mold resin MRJ is of a rectangular shape and has terminals PT arranged along both sides thereof. FIG. 72 representatively shows lead terminals arranged along one side of mold resin MRJ.
Each lead terminal PT is normally of a gull-wing lead (an L lead) shape and is soldered on a board. Since lead terminal PT is not inserted into a through hole formed in the board, TSOP can be arranged on each surface of the board.
TSOP is on the order of 1 mm in thickness and is extremely thin. In addition, lead terminal PT is of a gull-wing shape, and therefore, superior in workability as compared with an SOJ (small outline with J leads) package having pin terminals PT of J lead shape, and a lead pitch can be made smaller.
As such a thin rectangular package having lead terminals PT arranged only along the long side thereof, there are also known, beside TSOP, an SVP (surface vertical package) which is a vertical surface mount device and a USOP (ultra small outline package) which is as thin as 0.5 mm. These packages are widely employed for assembling semiconductor memory devices.
In applications such as portable equipment, high density mounting is required. In such applications, an MCP (multi chip package) having a plurality of chips arranged therein is employed, instead of an SCP (single chip package), such as TSOP, having one chip arranged therein. As MCP, there are known an MCM (multi chip module) type MCP having a plurality of chips assembled in an interposer (substrate) two-dimensionally and a stacked type MCP having a plurality of semiconductor chips stacked on an interposer.
FIG. 73 is a schematic diagram showing the configuration of conventional stacked type MCP. In FIG. 73, stacked type MCP, semiconductor chips CH3 to CH1 are stacked on an interposer IPS. A supporting insulator ISD1 is arranged between semiconductor chips CH1 and CH2. A supporting insulator ISD2 is arranged between semiconductor chips CH2 and CH3. A supporting insulator ISD3 is arranged between interposer IPS and semiconductor chip CH3.
Through holes are formed in supporting insulator ISD3 and pads formed on semiconductor chip CH3 are connected through solder balls SLS to pads PD formed on interposer IPS.
As for semiconductor chip CH1, solder balls (micro bumps) SLS formed on the pads are electrically connected to pads PD formed on interposer IPS through bonding wires BW1a and BW1b. 
Similarly, as to semiconductor chip CH2, solder balls SLS formed on the pads are electrically connected to pads, not shown, formed on interposer IPS through bonding wires BW2a and BW2b. Wiring is made in interposer IPS and pads PD formed on interposer IPS are connected to bump balls BPS formed on the rear surface of IPS. Internal interconnecting wires may be formed in a supporting insulator ISD.
Semiconductor chips CH1 to CH3 and pads PD are sealed by mold resin MRJ.
As shown in FIG. 73, since stack type MCP has a plurality of semiconductor chips CH1 to CH3 stacked and assembled therein, it is possible to mount a plurality of chips with a small occupation area.
FIG. 74 is a schematic diagram showing the rear surface of MCP. On the rear surface of MCP, bump balls BPS are arranged in an array. These bump balls BPS are connected to solder balls formed on a mounting board. Therefore, MCP employs bump balls BPS, rather than lead terminals, so as to electrically connect semiconductor chips CH1 to CH3 to an external device. By arranging bump balls BPS in an array form on the rear surface of mold resin MRJ, a large number of bump balls can be arranged and the number of input and output signals/data can be increased. This package having bump balls arranged in an array form is referred to as “BGP (ball grid package)”. MCP is, therefore, a family member of BGP.
A semiconductor memory device is now considered as one example of the semiconductor circuit device. In the semiconductor memory device, a word configuration is changed by setting a bonding pad potential by mask interconnection or bonding wire connection, so as to cover different word configurations with the same chip configuration. The internal configuration is the same, but only the number of data input/output circuits to be used is different. Thus, it is possible to cover a plurality of types of word configurations with chip configuration of a kind, improving manufacturing/design efficiency.
However, pad arrangement is different for different package. It is, therefore, necessary to optimize the layout of the internal circuitry of a semiconductor chip individually according to each package. Conventionally, the arrangement of pads is optimized differently for BGP (ball grid package) and TSOP of SCP, for example.
In the semiconductor memory device, in particular, unlike an embedded DRAM (dynamic random access memory) which is integrated on a semiconductor chip together with a logic circuit, the number of input/output data bits is small (32 bits) and TSOP is normally employed as an assembling package. In case of the semiconductor memory device, an LOC (lead on chip) structure is conventionally, normally used for such TSOP. In LOC structure, pads are arranged in the central portion of a chip to decrease a chip area.
In BGP, such an LOC structure is not employed, but wire bonding, TAB (tape automated bonding) and flip chip bonding and other (s) are employed for making electrical connections between chip pads and package terminals (bump balls).
Therefore, semiconductor memory chips having a pad arrangement optimized for such a TSOP package cannot be applied to BGP.
Furthermore, depending on a processing purpose, the storage capacity required for a memory differs. For example, one memory chip of 128 M bits is required for an application of a simple processing, while a memory of the storage capacity of 256 M bits is required for an application of processing image and audio data in portable equipment.
To implement a memory of 256 M bits using existing memory chips each having a storage capacity of 128 M bits, it is sufficient to employ two memories each of 128 M bits, simply. In this case, if the required storage capacity is to be satisfied using two TSOPs, the area of memory chips disadvantageously increases to obstruct down-sizing of the portable equipment.
Possible consideration to avoid such obstruction is such that memory chips with the same configuration as those for TSOP are applied to MCP to implement a memory of 256 M bits. However, since MCP is of BGP, the memory chips suited for TSOP cannot be applied to MCP.
Moreover, a specification required for a memory of 128 M bits differs from that required for a memory of 256 M bits in some cases. For instance, as to a memory of 256 M bits, if a word structure is of 16 bits, an 8K refresh cycle is set. In contrast, for a memory of 128 M bits with a word structure of 16 bits, the refresh cycle is set to a 4K refresh cycle. Therefore, it is impossible to implement a memory of 256 M bits by simply using two memory chips each having a storage capacity of 128 M bits.